Digital logic circuits may be described by the type of logic they use. For example, one type, known as combinational or combinatorial logic, generates one or more outputs as a function only of the current input or inputs. Another type of logic circuits, known as state logic, typically produces the output or outputs as a function of what is known as a present state vector. The present state vector is typically stored in storage elements, such as flip-flops and data storage media, and is typically influenced by several factors, including the current input or inputs and the history of inputs.
State logic circuits also typically contain circuitry that generates what is known as a next state vector, which typically in turn determines the output or outputs generated. Like the present state vector, the next state vector is typically stored in storage elements. In addition, state logic circuits may contain combinational logic elements, such as logic gates.
State logic circuits can be further described by the way in which they store the present and next state vectors. One type of state logic circuit, known as static state logic, typically stores information on arrays of memory elements, such as flip-flops. This approach is relatively simple, but static state logic circuits are often relatively expensive due to the amount of chip real estate required for their implementation. Dynamic state logic circuits, which may include static state logic elements, typically include elements that store information as electrical charges on points in the circuit known as nodes. Such nodes are typically capable of assuming a state of high impedance that enables them to hold electrical charges. Storing information as electrical charges leads to greater cost- and space-efficiency compared to static state logic circuits, but dynamic state logic circuits are typically refreshed periodically.
During the refreshing process, data is read from and rewritten to the nodes. Refreshing is typically achieved through a "clocking" process, by which the circuit cycles through a series of nodes or groups of nodes and refreshes the nodes in succession. This process is typically controlled by a clock signal.
In testing of dynamic state logic circuits, it is desirable to be able to turn off the clock signal. Without clocking, however, the electrical charges on the nodes may degrade to indeterminate levels that do not correspond clearly to either logic level. Such degradation results from several physical phenomena, including leakage currents. When degradation occurs, the nodes contain charges that do not clearly represent either the high logic state or the low logic state. Rather, the charge levels fall between the high logic charge threshold and the low logic charge threshold. As a result, the behavior of the logic circuit in response to these indeterminate charge levels is difficult to predict. Furthermore, the quiescent currents existing even in the absence of logic signals may rise to unacceptable levels, potentially leading to device failure.
In addition, in order to test dynamic logic circuits, it is often desirable to readily initialize the circuits to known states. Such initialization may present difficulties with state logic, however, because the output of a state logic circuit typically depends on the history of inputs in addition to the current input or inputs. For example, a flip-flop typically has a master stage and a slave stage. The master stage samples a data signal during one phase of the clock signal and changes its logic state accordingly. During the other phase of the clock signal, the slave stage assumes the logic state held by the master stage. The output of a conventional edge-triggered flip-flop changes during an effective edge of the clock signal, during which the clock signal changes from one state to the other. For example, the output of a positive edge-triggered flip-flop changes when the clock signal transitions from the low logic state to the high logic state. Consequently, if the input to such a flip-flop changes before the next clock cycle, the output and input of the flip-flop will not be the same. Therefore, the output is a function of the history of inputs. Because the history of inputs is not always known, it is difficult to predict the output at a given time based only on knowledge of the input at that time.
The concerns of degradation and testability have been addressed through the use of crowbar reset transistors, which typically discharge high-impedance nodes asynchronously, regardless of the state of the clock signal. This solution, however, presents difficulties because crowbar reset can further degrade performance with additional capacitive and leakage loading on the circuit by the additional transistors. Other difficulties, such as permanent damage to the circuit, may arise, for example, if a node is coupled to both the power supply and ground simultaneously. Crowbar reset must therefore be managed carefully to avoid these problems. Furthermore, this approach typically requires a dedicated transistor for each node, increasing the amount of device space required.